The present invention relates to a data reading circuit including a circuit for equalizing potentials applied to a pair of data buses for the transfer of data with each other, and particularly to a technique for adjusting an equalizing with each other voltage for equalizing potentials applied to a pair of data buses.
As a data reading circuit including a circuit for equalizing potentials applied to a pair of data buses (a pair of bit lines) with each other, there is known one which has been disclosed in Japanese Laid-Open Patent Publication No. 63-166090, for example.
The disclosed data reading circuit has an equalizing circuit for precharging each of a pair of bit lines to about a VDD level in response to a precharge signal and for equalizing potentials applied to the pair of bit lines with each other, and two pull-up transistors for supplying about VDD levels to the pair of bit lines respectively at all times.
The two pull-up transistors prevent the difference between the potential applied to one of the pair of bit lines and the potential applied to the other thereof from excessively increasing.